Speed-up of high accuracy analog test stimulus optimization

Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the innnite domain of possible values and the parameter deviations are among the major diiculties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations , but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In section I a review of the state of the art is presented, section II introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and conclusions are given in sections III and IV.